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ds013 (v1.8) april 19, 2001 www.xilinx.com 1 preliminary product specification 1-800-255-7778 ? 2001 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. features ? lowest power 256 macrocell cpld 7.5 ns pin-to-pin logic delays system frequencies up to 140 mhz 256 macrocells with 6,400 usable gates available in small footprint packages - 144-pin tqfp (120 user i/o pins) - 208-pin pqfp (164 user i/o) - 256-ball fbga (164 user i/o) - 280-ball cs bga (164 user i/o) optimized for 3.3v systems - ultra low power operation - 5v tolerant i/o pins with 3.3v core supply - advanced 0.35 micron five layer metal eeprom process - fzp? cmos design technology advanced system features - in-system programming - input registers - predictable timing model - up to 23 clocks available per function block - excellent pin retention during design changes - full ieee standard 1149.1 boundary-scan (jtag) - four global clocks - eight product term control terms per function block fast isp programming times port enable pin for additional i/o 2.7v to 3.6v supply voltage at industrial grade voltage range programmable slew rate control per output security bit prevents unauthorized access refer to xpla3 family data sheet (ds012) for architecture description description the XCR3256XL is a 3.3v, 256 macrocell cpld targeted at power sensitive designs that require leading edge program- mable logic solutions. a total of 16 function blocks provide 6,400 usable gates. pin-to-pin propagation delays are 7.5 ns with a maximum system frequency of 140 mhz. totalcmos? design technique for fast zero power xilinx offers a totalcmos cpld, both in process technol- ogy and design technique. xilinx employs a cascade of cmos gates to implement its sum of products instead of the traditional sense amp approach. this cmos gate imple- mentation allows xilinx to offer cplds that are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. refer to figure 1 and table 1 showing the i cc vs. frequency of our XCR3256XL totalcmos cpld (data taken with 16 up/down, loadable 16-bit counters at 3.3v, 25 c). 0 XCR3256XL 256 macrocell cpld ds013 (v1.8) april 19, 2001 014 preliminary product specification r
XCR3256XL 256 macrocell cpld 2 www.xilinx.com ds013 (v1.8) april 19, 2001 1-800-255-7778 preliminary product specification r dc electrical characteristics over recommended operating conditions (1) figure 1: XCR3256XL typical i cc vs. frequency at v cc = 3.3v, 25 c table 1: typical i cc vs. frequency at v cc = 3.3v, 25 c frequency (mhz) 0 1 10 20 40 60 80 100 120 140 ty p i c a l i cc (ma) 0.02 0.91 8.87 17.7 34.8 51.5 68 84.2 100.1 116.6 symbol parameter test conditions min. max. unit v oh (2) output high voltage i oh = ? 8 ma 2.4 - v v ol output low voltage for 3.3v outputs i ol = 8 ma - 0.4 v i il input leakage current v in = gnd or v cc ? 10 10 a i ih i/o high-z leakage current v in = gnd or v cc ? 10 10 a i ccsb standby current v cc = 3.6v - 100 a i cc dynamic current (3,4) f = 1 mhz - 2 ma f = 50 mhz - 60 ma c in input pin capacitance (5) f = 1 mhz - 8 pf c clk clock input capacitance (5) f = 1 mhz 5 12 pf c i/o i/o pin capacitance (5) f = 1 mhz - 10 pf notes: 1. see xpla3 family data sheet (ds012) for recommended operating conditions. 2. see figure 2 for output drive characteristics of the xpla3 family. 3. see table 1 , figure 1 for typical values. 4. this parameter measured with a 16-bit, loadable up/down counter loaded into every function block, with all outputs disabled a nd unloaded. inputs are tied to v cc or ground. this parameter guaranteed by design and characterization, not testing. 5. typical values, not tested. 0 20 40 60 80 100 120 140 0 20 40 60 80 100 120 140 160 frequency (mhz) typical icc (ma)
XCR3256XL 256 macrocell cpld ds013 (v1.8) april 19, 2001 www.xilinx.com 3 preliminary product specification 1-800-255-7778 r ac electrical characteristics over recommended operating conditions (1,2) figure 2: typical i/v curve for the xpla3 family symbol parameter -7 -10 -12 unit min. max. min. max. min. max. t pd1 propagation delay time (single p-term) - 7.0 - 9.0 - 10.8 ns t pd2 propagation delay time (or array) (3) - 7.5 - 10.0 - 12.0 ns t co clock to output (global synchronous pin clock) - 4.5 - 5.8 - 6.9 ns t suf (4) setup time fast 2.0 - 2.5 - 3.0 - ns t su (4) setup time 4.8 - 6.5 - 7.9 - ns t h (4) hold time 0-0-0-ns t wlh (4) global clock pulse width (high or low) 3.0 - 4.0 - 5.0 - ns tt plh (4) p-term clock pulse width 4.5 - 6.0 - 7.5 - ns t r (4) input rise time - 20 - 20 - 20 ns t l (4) input fall time - 20 - 20 - 20 ns f system (4) maximum system frequency - 140 - 105 - 88 mhz t config (4) configuration time (5) -40-40-40 s t poe (4) p-term oe to output enabled - 9.0 - 11.0 - 13.0 ns t pod (4) p-term oe to output disabled (6) - 9.0 - 11.0 - 13.0 ns t pco (4) p-term clock to output - 8.0 - 10.3 - 12.4 ns t pao (4) p-term set/reset to output valid - 9.0 - 11.0 - 13.0 ns notes: 1. specifications measured with one output switching. 2. see xpla3 family data sheet (ds012) for recommended operating conditions. 3. see figure 4 for derating. 4. these parameters guaranteed by design and/or characterization, not testing. 5. typical current draw during configuration is 10 ma at 3.6v. 6. output c l = 5 pf. 0 0 1 0 2 0 30 4 0 50 60 7 0 80 90 1 00 0 . 5 1 1. 5 2 2. 5 3 3 . 5 4 4. 5 5 volt s i o l ( 3.3v ) i o h ( 3.3v ) i o h ( 2.7v ) m a ds012 _ 10 _ 04190 1
XCR3256XL 256 macrocell cpld 4 www.xilinx.com ds013 (v1.8) april 19, 2001 1-800-255-7778 preliminary product specification r internal timing parameters (1,2) symbol parameter -7 -10 -12 unit min. max. min. max. min. max. buffer delays t in input buffer delay - 2.5 - 3.3 - 4.0 ns t fin fast input buffer delay - 2.2 - 2.8 - 3.3 ns t gck global clock buffer delay - 1.0 - 1.3 - 1.5 ns t out output buffer delay - 2.5 - 2.8 - 3.3 ns t en output buffer enable/disable delay - 4.5 - 5.2 - 6.0 ns internal register and combinatorial delays t ldi latch transparent delay - 1.3 - 1.6 - 2.0 ns t sui register setup time 0.8 - 1.0 - 1.2 - ns t hi register hold time 4.0 - 5.5 - 6.7 - ns t ecsu register clock enable setup time 2.0 - 2.5 - 3.0 - ns t echo register clock enable hold time 3.0 - 4.5 - 5.5 - ns t coi register clock to output delay - 1.0 - 1.3 - 1.6 ns t aoi register async. s/r to output delay - 2.0 - 2.0 - 2.2 ns t rai register async. recovery - 5.0 - 7.0 - 8.0 ns t logi1 internal logic delay (single p-term) - 2.0 - 2.5 - 3.0 ns t logi2 internal logic delay (pla or term) - 2.5 - 3.5 - 4.2 ns feedback delays t f zia delay - 2.8 - 3.7 - 4.4 ns time adders t logi3 fold-back nand delay - 6.0 - 8.0 - 9.5 ns t uda universal delay - 2.0 - 2.5 - 3.0 ns t slew slew rate limited delay - 4.0 - 5.0 - 6.0 ns notes: 1. these parameters guaranteed by design and/or characterization, not testing. 2. see xpla3 family data sheet (ds012) for the timing model.
XCR3256XL 256 macrocell cpld ds013 (v1.8) april 19, 2001 www.xilinx.com 5 preliminary product specification 1-800-255-7778 r switching characteristics figure 3: ac load circuit v cc v out v in c1 r1 r2 s1 s2 ds013_03_050200 component values r1 390 ? r2 390 ? c1 35 pf measurement s1 s2 t poe (high) t poe (low) t p open closed closed open closed closed note: for t pod , c1 = 5 pf figure 4: derating curve for t pd2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 7.0 7.1 7.2 7.3 7.4 7.5 124816 ds013_04_042800 number of adjacent outputs switching (ns) figure 5: voltage waveform 90% 10% 1.5 ns 1.5 ns ds017_05_042800 +3.0v 0v measurements: all circuit delays are measured at the +1.5v level of inputs and outputs, unless otherwise specified. t r t l
XCR3256XL 256 macrocell cpld 6 www.xilinx.com ds013 (v1.8) april 19, 2001 1-800-255-7778 preliminary product specification r pin descriptions table 2: XCR3256XL user i/o pins tq144 pq208 ft256 cs280 total user i/o pins 120 164 164 164 table 3: XCR3256XL i/o pins function block macro- cell tq144 pq208 ft256 cs280 1 1 106 6 c16 e18 12-7f12e19 1 3 104 (1) 8d16f15 141039e14f17 1510210e15f18 16--- - 17--- - 18--- - 19--- - 110-- - - 111-- - - 1 12 101 11 f13 f19 1 13 100 12 e16 g16 1149913f14g17 1 15 - 15 f15 g19 116-16g12h16 2 1 107 4 e13 b19 2 2 108 3 d15 b18 2 3 - 206 c13 b17 2 4 - 205 a14 a18 2 5 109 204 e11 a17 26--- - 27--- - 28--- - 29--- - 210-- - - 211-- - - 2 12 110 203 a13 c16 2 13 111 202 d12 a16 2 14 - 201 b13 e15 2 15 112 199 c12 d15 2 16 113 198 a12 a15 3 1 98 17 g15 h17 3 2 97 18 g13 h18 3 3 96 19 f16 h19 3 4 94 20 g14 j16 3 5 93 21 g16 j17 36--- - 37--- - 38--- - 39--- - 310--- - 311--- - 3129222h13j18 313-24h12k16 3149125h15k17 3159026h14k18 316-27h16l16 4 1 114 197 d11 e14 4 2 116 196 a11 d14 4 3 117 195 e10 a14 4 4 - 194 b12 c13 4 5 118 193 c11 b13 46--- - 47--- - 48--- - 49--- - 410--- - 411--- - 4 12 119 192 b11 a13 4 13 120 190 a10 a12 4 14 121 189 (1) c10 (1) c12 (1) 4 15 - 188 a9 b12 4 16 122 187 d9 d12 5189 (1) 28 j14 l17 5 2 - 29 j15 l18 5 3 88 30 (1) j13 (1) l19 (1) 5 4 87 31 j16 m16 5 5 86 33 l14 m18 ta ble 3 : XCR3256XL i/o pins (continued) function block macro- cell tq144 pq208 ft256 cs280
XCR3256XL 256 macrocell cpld ds013 (v1.8) april 19, 2001 www.xilinx.com 7 preliminary product specification 1-800-255-7778 r 56--- - 57--- - 58--- - 59--- - 510-- - - 511-- - - 5128434k15m17 513-35k14n16 5148336k16n19 5158237k13n18 5 16 - 38 l15 n17 61-78r9u10 6 2 55 77 n9 t10 6 3 56 76 t10 w11 64-73p10u11 6 5 60 71 r10 t11 66--- - 67--- - 68--- - 69--- - 610-- - - 611-- - - 6126170t11w12 6136269n10u12 6146368p11t12 615-67m10v13 6166566r11u13 7 1 81 39 k12 p16 7 2 - 40 l16 p18 7 3 80 42 m15 r19 7 4 79 43 n15 r16 7 5 78 44 l13 r18 76--- - 77--- - 78--- - 79--- - 710-- - - table 3: XCR3256XL i/o pins (continued) function block macro- cell tq144 pq208 ft256 cs280 711--- - 7127745m16r17 713-46m14r15 7147547n16t17 7157448l12t16 716-49p15u19 8 1 66 65 t12 t13 8 2 67 64 r12 w14 8 3 68 62 n11 t14 8 4 69 61 t13 r14 85-60p12w15 86--- - 87--- - 88--- - 89--- - 810--- - 811--- - 8127059r13u15 813-58m11v15 8147157t14t15 815-56n12v16 8167255r14w17 9 1 2 153 d3 b1 9 2 1 154 c1 c3 9 3 - 159 b4 a4 9 4 - 160 e6 b5 9 5 143 161 a4 c5 96--- - 97--- - 98--- - 99--- - 910--- - 911--- - 9 12 - 162 c5 a5 9 13 142 163 b5 e6 9 14 141 164 d6 d6 9 15 140 166 a5 b6 ta ble 3 : XCR3256XL i/o pins (continued) function block macro- cell tq144 pq208 ft256 cs280
XCR3256XL 256 macrocell cpld 8 www.xilinx.com ds013 (v1.8) april 19, 2001 1-800-255-7778 preliminary product specification r 9 16 139 167 c6 a6 10 1 4 (1) 151 d1 d2 10 2 - 150 e4 d1 10 3 5 149 d2 e3 10 4 6 148 e3 e2 10 5 7 147 e1 e4 10 6 - - - - 10 7 - - - - 10 8 - - - - 10 9 - - - - 10 10 - - - - 10 11 - - - - 10 12 8 146 f4 e1 10 13 - 145 f1 f5 10 14 9 144 g5 f3 10 15 10 142 e2 f4 10 16 11 141 f3 g3 11 1 - 168 b6 d7 11 2 - 169 e7 c7 11 3 138 170 a6 b7 11 4 - 171 d7 a7 11 5 137 172 b7 c8 11 6 - - - - 11 7 - - - - 11 8 - - - - 11 9 - - - - 11 10 - - - - 11 11 - - - - 11 12 136 173 c7 b8 11 13 134 175 c8 c9 11 14 133 176 (1) a7 (1) b9 (1) 11 15 132 177 d8 d10 11 16 131 178 b8 c10 12 1 - 140 f2 g2 12 2 - 139 g4 g1 12 3 12 138 g1 g4 12 4 14 137 h1 h1 table 3: XCR3256XL i/o pins (continued) function block macro- cell tq144 pq208 ft256 cs280 12 5 15 136 h4 h3 12 6 - - - - 12 7 - - - - 12 8 - - - - 12 9 - - - - 12 10 - - - - 12 11 - - - - 12 12 16 135 g2 h2 12 13 - 133 j1 j2 12 14 18 132 j3 j3 12 15 19 131 h2 k2 12 16 - 130 j5 k3 13 1 - 79 p9 w10 13 2 54 80 t9 t9 13 3 53 81 p8 u9 13 4 - 84 r8 t8 13 5 49 86 n8 t7 13 6 - - - - 13 7 - - - - 13 8 - - - - 13 9 - - - - 13 10 - - - - 13 11 - - - - 13 12 48 87 t8 w7 13 13 47 88 p7 v7 13 14 46 89 r7 u7 13 15 - 90 p6 w6 13 16 45 91 t7 t6 14 1 20 (1) 129 j2 k4 14 2 - 128 j4 l1 14 3 21 127 (1) k1 (1) l2 (1) 14 4 22 126 k3 l3 14 5 23 124 k2 m1 14 6 - - - - 14 7 - - - - 14 8 - - - - 14 9 - - - - ta ble 3 : XCR3256XL i/o pins (continued) function block macro- cell tq144 pq208 ft256 cs280
XCR3256XL 256 macrocell cpld ds013 (v1.8) april 19, 2001 www.xilinx.com 9 preliminary product specification 1-800-255-7778 r 14 10 - - - - 14 11 - - - - 14 12 25 123 l1 m3 14 13 - 122 k4 m4 14 14 26 121 l3 n1 14 15 27 120 k5 n2 14 16 28 119 m1 n3 15 1 44 92 n7 v6 15 2 43 93 r6 u6 15 3 42 95 m7 r6 15 4 41 96 t5 w5 15 5 40 97 t6 t5 15 6 - - - - 15 7 - - - - 15 8 - - - - 15 9 - - - - 15 10 - - - - 15 11 - - - - 15 12 - 98 r5 v5 15 13 39 99 n6 u5 15 14 38 100 t4 w4 15 15 - 101 p5 u4 15 16 37 102 r4 w3 16 1 - 118 l2 p1 16 2 - 117 m2 p2 16 3 29 115 m3 p4 16 4 30 114 n2 r3 16 5 31 113 l5 r2 16 6 - - - - 16 7 - - - - 16 8 - - - - 16 9 - - - - 16 10 - - - - 16 11 - - - - 16 12 32 112 p1 r4 16 13 - 111 m4 t3 16 14 34 110 r1 u1 table 3: XCR3256XL i/o pins (continued) function block macro- cell tq144 pq208 ft256 cs280 16 15 35 109 n3 v1 16 16 36 108 t1 u2 notes: 1. jtag pins. ta ble 3 : XCR3256XL i/o pins (continued) function block macro- cell tq144 pq208 ft256 cs280
XCR3256XL 256 macrocell cpld 10 www.xilinx.com ds013 (v1.8) april 19, 2001 1-800-255-7778 preliminary product specification r table 4: XCR3256XL global, jtag, port enable, power, and no connect pins pin type tq144 pq208 ft256 cs280 in0 / clk0 128 181 b9 a10 in1 / clk1 127 182 a8 d11 in2 / clk2 126 183 c9 c11 in3 / clk3 125 184 b10 b11 tck 89 30 j13 l19 tdi 4 176 a7 b9 tdo 104 189 c10 c12 tms 20 127 k1 l2 port_en 13 (1) 116 (1) n1 (1) p3 (1) vcc 24, 50, 51, 58, 73, 76, 95, 115, 123, 130, 144 5, 23, 41, 63, 74, 83, 85, 107, 125, 143, 165, 179, 186, 191 e8, e9, f7, f8, f9, f10, g6, g11, h5, h6, h11, j6, j11, j12, k6, k11, l7, l8, l9, l10, m8, m9 a11, b10, c6, c14, d13, d17, f2, j19, l4, p15, t18, u8, u14, v2, v9, v11 gnd 3, 17, 33, 52, 57, 59, 64, 85, 105, 124, 129, 135 14, 32, 50, 72, 75, 82, 94, 134, 152, 174, 180, 185, 200 e5, f6, f11, g7, g8, g9, g10, h7, h8, h9, h10, j7, j8, j9, j10, k7, k8, k9, k10, l6, l11 e5, e7, e8, e9, e10, e11, e12, e13, g5, g15, h5, h15, j5, j15, k5, k15, l5, l15, m5, m15, n5, n15, r7, r8, r9, r10, r11, r12, r13 no connects - 1, 2, 51, 52, 53, 54, 103, 104, 105, 106, 155, 156, 157, 158, 207, 208 a1, a2, a3, a15, a16, b1, b2, b3, b14, b15, b16, c2, c3, c4, c14, c15, d4, d5, d10, d13, d14, e12, f5, g3, h3, l4, m5, m6, m12, m13, n4, n5, n13, n14, p2, p3, p4, p13, p14, p16, r2, r3, r15, r16, t2, t3, t15, t16 a1, a2, a3, a8, a9, a19, b2, b3, b4, b14, b15, b16, c1, c2, c4, c15, c17, c18, c19, d3, d4, d5, d8, d9, d16, d18, d19, e16, e17, f1, f16, g18, h4, j1, j4, k1, k19, m2, m19, n4, p5, p17, p19, r1, r5, t1, t2, t4, t19, u3, u16, u17, u18, v3, v4, v8, v10, v12, v14, v17, v18, v19, w1, w2, w8, w9, w13, w16, w18, w19 notes: 1. port enable is brought high to enable jtag pins when jtag pins are used as i/o. see family data sheet for full explanation.
XCR3256XL 256 macrocell cpld ds013 (v1.8) april 19, 2001 www.xilinx.com 11 preliminary product specification 1-800-255-7778 r ordering information revision history the following table shows the revision history for this document component compatibility pins 144 208 256 280 type plastic tqfp plastic pqfp plastic fbga plastic bga code tq144 pq208 ft256 cs280 XCR3256XL -7 c c c c -10 c, i c, i c, i c, i -12 c, i c, i c, i c, i date version revision 01/21/00 1.0 initial xilinx release. 02/10/00 1.1 updated pinout table. 05/03/00 1.2 minor updates and added boundary scan to pinout table. 11/20/00 1.3 updated pinout tables; corrected note in ta ble 4 to read: "port enable pin is brought high". 12/11/00 1.4 updated specifications and pinout tables. 01/17/01 1.5 removed timing model. 03/05/01 1.6 added 256-ball fine-pitch ball grid array package. 04/11/01 1.7 added typical i/v curve, figure 2 ; added table 2 : total user i/o; changed v oh spec. 04/19/01 1.8 updated typical i/v curve, figure 2 : added voltage levels. XCR3256XL -7 pq 208 c example: temperature range number of pins package type device type speed grade device ordering options speed package temperature -12 12 ns pin-to-pin delay tq144 144-pin thin quad flat pack c = commercial t a = 0 c to + 70 c v cc = 3.0v to 3.6v -10 10 ns pin-to-pin delay pq208 208-pin plastic quad flat package i = industrial t a = ? 40 c to +85 c v cc = 2.7v to 3.6v -7 7.5 ns pin-to-pin delay ft256 256-ball fine-pitch ball grid array cs280 280-ball chip scale package

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